1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that has a plurality of chip areas each having a semiconductor chip formed therein and a peripheral area connecting the chip areas to each other.
2. Description of the Related Art
In order to improve yields and reduce chip cost, a semiconductor memory such as a DRAM (Dynamic Random Access Memory) has a redundancy memory cell (redundancy circuit) for relieving a defect in a memory cell during a fabrication process. The defect in the memory cell is relieved by replacing the defective memory cell by the redundancy memory cell during a test process.
Generally, a semiconductor memory having a redundancy memory cell has fuse circuits storing an address of a defective memory cell. In case of directly cutting off fuse portions in the fuse circuits, it is necessary to consider how laser beam irradiation to the fuse portions gives influence on their ambient internal circuits. Specifically, it is necessary to limit the arrangement of the ambient internal circuits. This lowers the degree of integration of the semiconductor memory, resulting in increased chip size.
In view of solving this problem, for example, Japanese Unexamined Patent Application Publication No. Sho 60-182150 has disclosed a semiconductor integrated circuit that adopts fuse circuits in which fuse portions are cut off by electric current and that has fuse cutting pads (pads for supplying the electric current to the fuse portions) in a scribe area. With this semiconductor integrated circuit, it is possible to realize highly integrated semiconductor memories, in other words, chip size reduction since no limitation has to be imposed on the arrangement of the ambient internal circuits and the fuse cutting pads are provided in the scribe area.